Design and implementation of the high-performance low-power MorphoSys reconfigurable processor

In recent years, there has been a remarkable growth of the portable computing and wireless communication devices market. Reducing power consumption is a key design goal for portable computing and communication devices that employ increasingly sophisticated and power-hungry signal processing techniques. The future of portable devices also demands an increasing support of multiple standards (e.g. CDMA), which by necessity requires a programmable implementation platform. All these arguments lead to the need of powerful programmable low-power computing systems. This work proposes MorphoSys, a high-performance low-power reconfigurable processor. The MorphoSys architecture consists of a reconfigurable component (RC Array), a general-purpose RISC processor (TinyRISC), and a high bandwidth memory interface. We discuss the MorphoSys architecture including the TinyRISC, the RC Array, and the data and configuration memories. We also present the detailed design implementation and the various aspects of physical layout of different sub-blocks of MorphoSys. The first-generation MorphoSys, M1, was implemented using CMOS 0.35 μm technology. It was designed to operate at 100 MHz of clock frequency. We provide simulation results of the M1 for some typical data-parallel applications (e.g. video compression and automatic target recognition). The results indicate that the MorphoSys system can achieve significantly better performance for most of these applications in comparison with other systems. Finally we propose several important low-power techniques for the second-generation MorphoSys. The design objective is to target portable computing and wireless communication applications. It will be demonstrated that reconfigurable architectures are an excellent vehicle to accomplish the high-performance low-power requirement of portable computing and wireless communication devices.