Design And Realization Of High-speed NoC Simulator Based On Multi-dimensional Arrays

Network-on-Chip (NoC) provides a novel solution for chip multi-processor (CMP). It solves the problem of high power consumption and low throughput within traditional bus-structured processors, and meanwhile it provides excellent scalability and parallelism. However, the design space of NoC is extremely large due to variety of topologies and algorithm, and large amount of parameters, which makes it difficult to build certain NoC models. As a result, a suitable NoC simulator is required to simplify the modeling and reduce the modeling time as well.This paper proposes a novel method to design a NoC simulator, and a high-speed NoC simulator, MABSIM, is realized. All the elements involving computing are presented by means of different multi-dimensional arrays, which means each module of the simulator as well as data transmission within the network is abstractly dealt by computing of arrays. We also realized the core and router nodes based on such data structures, and provided the users with variable of configurations as well as considerable scalabilities. Beside these characteristics, MABSIM is able to accelerate execution taking advantage of pthreads, which parallel the data transmission between node pairs and makes it competent to model a large-scale NoC model which composes of thousands of cores.For validations, MABSIM was compared with a common-use simulator, Graphite, under the same configurations. We use SPLASH-2as a benchmark, and compare the result and execution time of the two simulator. Memory consumption is also analyzed in the experiment.