Energy Efficiency And Reliability Optimization Methods For Multi-Core System-On-Chip

With the progress of integrated circuit technology and the development of computer technology, multi-core has become the mainstream architecture to build processors. How-evcr,due to the improvement of integration, energy efficiency and reliability of the chip has become the two major issues concerned in the development of itself. On one hand, with the progress of the integrated circuit technology, the power density of the chip is also increasing. High power consumption is not only wasting huge energy, but also de-creases the reliability of the system because of the thermal problems caused by the power density. On the other hand, with the scaling of the circuit, the physical failure probability of the chip is also getting bigger and bigger. This issue also leads to dramatic decrease the reliability of whole system. So this dissertation focuses on how to improve the energy efficiency and reliability of multi core system on chip from four key aspects:1.The energy efficiency optimization of multi-core system on chip based on shared memory mechanism is studied, a power consumption control method based on memory access delay model and DVFS technology is proposed. The method could calculate the voltage/frequency value of the processors and the un-core units directly by the preset model and the power control rules, thus the real implementation of this method could relatively simple and efficient. Compared with other method, the control accuracy of this method could be much higher, and the energy consumption of the system controlled by this method is further reduced by 6.8%-7.9%.2.This paper also studies the effect of dynamic mapping algorithm on energy ef-ficiency of the communication centric multi-core system on chip, and proposes an im-proved dynamic mapping algorithm based on the classical mapping algorithm, CoNA. Because of the improving, the new algorithm takes full account of the influence of dif-ferent tasks on the transmission delay and energy consumption. Using the algorithm to achieve the task of dynamic mapping, average data transmission delay is reduced by 2 to 3 Cycle, the total energy consumption decreased by 2.47%-8.30% compared with classical CoNA algorithm.3.A non-blocking online testing strategy is proposed to improving the classical on-line built-in self-test (BIST), and multiple routers could be tested simultaneously at high speed without blocking or dropping packets which would reduce die Energy Efficiency of the whole system on chip. This testing strategy could be chosen as a real-time testing method to capture the transient or intermittent fault of network based multi-core system on chip because the operation of the chips would not be stopped while the network is tested. The reliability of the chips would be increased.4.A new fault tolerant mechanism for "illegal turn faults" in NoCs is proposed in this thesis. The spatial redundancy of NoCs and adaptive routing algorithm are used to tolerate this kind of faults. Compared with dual mode redundancy, the delivery rate could be significantly improved new method. This method would not only improve the reliability of the multi-core system but also reduce the extra power consumption of data retransmission.