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The Design Of Photoelectric Sorter Detection System Based On FPGA

Posted on:2008-04-21Degree:MasterType:Thesis
Country:ChinaCandidate:Y QiaoFull Text:PDF
GTID:2178360242467108Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
Photoelectric sorter is a high-tech device, which distinguish the materials' quality with photoelectricity and remove the inferior stuffs with the help of compressed air. Because of the unique technical and sort feature, the device is widely used in detecting and grading of grainy materials, which can effectively improve materials' quality and the automatization level of machining technology, so, it gains great social and economic benefits. Therefore, the study on the photoelectric sorter is of great importance and practical significance.The thesis mainly studies the detection system of photoelectric sorter and designs the photoelectric detection system based upon XC3S200 FPGA and high-rate linear CCD. The function of detection system scans the falling grainy materials in high speed by CCD sensor. The CCD output signal through the image digitizer which includes the image signal conditioning, A/D converter is high-rate processed by FPGA. Then the detection system sends out removed signals.The hardware design of detection system includes the core circuit of FPGA; drive circuit of CCD; the interface circuit of digitizer; communication circuit. Printed circuit board is designed following request.The software design of detection system includes the driving time sequence design of CCD by DCM; the control interface and CDS time sequence of XRD98L59; constituting communication protocols with main control system and implementing data message filter; acquiring image data and implementing median filter; image binarization and the position of infested objects recognition; implementing delay time adjusting of detected signals by BlockRAM; the time sequence of the air gun control system; the driving time sequence for detecting show circuit; adjusting the position of CCD pixel; storaging the digital image data of CCD.In this paper, the hardware description is realized in Verilog language. The design of system software takes top-down metheod and the way of modularization. Using the platform of ISE8.2, Synplify Pro8.1, Modelsim6.1 software has completed the simulation, synthesis, implementation and configuration of every module. The program is downloaded in XC3S200 and debugged in-line. The experimental results prove detection system has accomplished driving of CCD, image acquisition, image pre-processing, image recognition and detection.
Keywords/Search Tags:Photoelectric Sorter, FPGA, CCD, Median Filter, Binarization
PDF Full Text Request
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