Design And Implementation Of Photoelectric Sorter Detection System

Currently, photoelectric sorters are widely used in detecting and grading of grainy materials, which can effectively improve materials' quality and the automatization level of machining technology, so, it gains great social and economic benefits.Sorting is a way to sort and remove infested objects by using photoelectrical technology. The most important part of sorting is the detection and identification of the differences between the infested and certified materials. This paper demonstrates a photoelectric detection system based upon high resolving power and low noise linear CCD to acquire image data, and uses XSC40XL FPGA by Xilinx as the core controller and processor to provide parallel high-rate image data processing, thus the need of real-time can be satisfied. The detection system can identify defects in size of 1 mm × 0.4mm, different species and off-color materials.The hardware design of detection system includes drive circuit design of high speed CCD camera; the image signal conditioning, sample and store circuit design; the selection of processor chip; communication circuit design for data transmit and power supply circuit design for the voltages that are required by the system. The hardware circuit is mainly designed based on high-speed LSI (Large Scale Integrated) circuits and multi-layer circuits. Because of this, the design has high reliability and the size of the PCB (Printed-Circuit Board) is small and matches the camera lenses and volume.Based on FPGA technology, this design realizes high frequency on dividing and multiplying control, CCD time sequence logical control, CCD image data sample and store, (7,3) cyclic code's encode and decode as well as 16-bit Circulation Redundancy Check. Besides, the design completes synchronous serial communication system based on self-defining protocol, furthermore, the design completes the sample image data acquisition and transmission after receiving collection command, and the system sends out removed signals according to image recognition rule and arithmetic.In this paper, the hardware description is totally realized in Verilog language. Using ISE 4.2 software has completed the simulation, synthesis, implementation and configuration of every circuit. The experimental results prove CCD has been driven and sample image have been acquired using image digitizer (XRD98L59) and exterior memories. Besides, detection system has accomplished a stable and reliable communication with the main controll system.