| Beginning from the 0.18um technology node, the so-called Sub-Wavelength Lithography has been widely used in semiconductor processes, in which feature size of manufactured IC is shorter than illumination wavelength. The adoption of Sub-Wavelength Lithography introduces differences between printed shapes on silicon wafer and the mask patterns. The distortion in pattern transfer may influence the functionality and performance of IC products and lower the production yield. Resolution Enhancement Technologies are now used in Sub-Wavelength Lithography circumstance to partially solve the incurring manufacturability problem. However, with the Sub-Wavelength Lithography continues extending to its physical limit, new kinds of problems on manufacturability and yield keep emerging. This is one of the most concerned issues for global IC industry and academia now.This dissertation tries to address and solve some of these new problems by studying the design and verification for IC manufacturability. Manufacturability problems produced by Sub-Wavelength Lithography are the major research objects. Basics of IC physical design and lithography are described. Conventional algorithms of lithographic simulation are described along with a report on software implementation of a projection imaging simulation system based on these algorithms. A new framework of lithographic modeling, which includes modeling of optical imaging, resist development and etch, is proposed and demonstrated by real modeling examples. Based on this framework, innovative fast simulation algorithms such as those for sparse point imaging and dense point imaging are developed. New OPC algorithms and a tool command framework is thereafter presented. New methodology and application of manufacturability check on layout pattern is introduced as well. In addition, a new flow of design for manufacturability of sub-100nm standard cells is presented with designed and manufactured examples.
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