Research And VLSI Implementation Of Reconfigurable Vision Processor

With the wide use of vision processing, the problems of computing efficiency in vision processor and various classification are getting serious. Based on the traditional vision processor, the reconfigurable vision processor adopts the configurable computing array to support the various classifications in vision processing. The configurable computing array can achieve parallel computing mode which tremendously improves the efficiency of vision classification. The architecture that is characterized by core of configurable array and cooperates with the heterogeneous and application specific accelerators will achieve high computing efficiency for the vision processor.Firstly, this dissertation focuses on the acceleration space and vision space in the vision processing, and designs the high efficient application specific architecture. For the computing of acceleration space, the configurable parallel architecture for integral histogram computing is proposed. By means of the strip based memory partitioning mechanism, the data throughput is improved. Meantime, by means of the strategy of data relative memory compression, the memory storing system is optimized. Compared with current works, the average computing speed is averagely improved by 2.9 times, and the power efficiency is averagely improved by 33.5%. For the memory accessing dependency problem in the computing of vision space computing, the data pattern of memory accessing is used to construct the system optimization model, and then the moving direction guided memory partitioning mechanism is proposed to improve the data throughput and data reusing. Compared with current works, this memory partitioning mechanism improves the memory accessing efficiency by 7.4 times.Secondly, for the problem of various classifications in vision processing, the mixed mode based reconfigurable computing architecture is proposed. This architecture not only solves the problem of various classifications, but also solves the load imbalance and useless computing for the window based searching in classification. By means of analyzing the computing topology of classification, the mixed computing modes including the parallel computing and software pipeline computing are designed. Compared with currents works, the average classification speed is improved by 33.75%, and the power efficiency is improved by 1.9 times.Lastly, based on the optimizations of the acceleration space, vision space and classification, two vision processors have been designed to implement the verification. The first one is the feature computing processor. It achieves the computing speed of 1080p@83fp with the constraint of computing average of 1000 FIRFAS features. Compared with the current works, the computation efficiency is improved by 2.95 times. The second one is the feature classification processor. It achieves the computing speed of 1080p@55fps with the constraint of recognizing average 1000 FIRFAS features. Compared with current works, the classification speed is improved by 1.29 times.