The Research On Two Dimension Array Based Reconfigurable Computing Design Space Exploration

Reconfigurable computing is a new paradigm for current high performance computing, which promises an intermediate trade-off between Application Specific Integrated Circuits (ASICs) and general purpose microprocessors. It provides powerful flexibility and performance. Because of its flexibility, reconfigurable computing architecture (RCA) has a vast design space, and it is a hard task to develop an optimized RCA for application specific domain. It exists very high value to search the design space of RCA and guide its design at an early stage. The dissertation emphasizes on the method for two dimension array based RCA design space exploration.In order to make design space exploration method independent on any concrete RCA, the dissertation defines a set of architectural parameters, which characterize different RCA. Based on it, hierarchical parameter model for RCA is presented, which not only characterizes RCA, but also describes the architecture's hierarchy. It has powerful flexibility, and can describe different two dimension array based RCA. Because mathematical abstraction for RCA is at high level, hierarchical parameter model accelerates RCA design space exploration.During design space exploration, each algorithm makes a different demand on connection resources of RCA. Connection resources estimation for RCA is discussed in the dissertation. By establishing stochastic model for application algorithm net routing, a method for estimating RCA connection resource based on stochastic model is given. It gives the number of each connection resources for application algorithm which is implemented on RCA, and the number of connection resources of RCA is determined.Reconfigurable processing element array is a key component in RCA. With analyzing reconfigurable array design space, the dissertation explains the algorithm to estimate area, time and power for reconfigurable array. By studying transformation, executing model and executing time of application algorithm, an algorithm with performance constraint for reconfigurable processing element array design space exploration is proposed. The algorithm produces the best reconfigurable processing element array for application domain, which meets the performance expectations of application algorithm.Memory architecture is an important component in RCA. Finally, the method for memory architecture design space exploration in RCA is discussed. The dissertationgives the maximum for local data memory size, configuration context memory size and the bandwidth of interface between local data memory and reconfigurable array. An algorithm with area constraint for memory architecture design space exploration is proposed, which acquires memory architecture with the best performance for application domain.