System Verilog Based System Level Verification And Design Of Denoise Module In Image Signal Processing System

As the first international telecommunication standard with independentintellectual property, the third generation mobile communication standard—TD-SCDMA is a milestone in China's history of telecommunication in the last century, and will have a far-going impact on the future. Joint-cell Image signal processing system is an important part of baseband chip in mobile phone. Its main job is to do lots of arithmetic to improve the image quality, It is an important part in multimedia design today, NSR module is a newly improved hardware accelerator in the second generation TD-SCDMA/GSM base-band chip of Spreadtrum Communications, Inc. The module is connected to ARM core through AHB bus using standard AMBA bus protocol. Verification of the module is aimed for finding and correcting the errors in chip design in the early stage, so that the risk of chip tape-out can be lowered, and the chip test can go more smoothly after taped out.As the complexity of chip design has grown up rapidly, in company with the challenges coming from technology and market issue, verification of the SoC (System on Chip) chip is becoming more and more difficult. Especially for mobile phone chip with more than 10M gates, the completion of the verification is extremely complicated, costing a large amount of manpower and time. Being unlike writing synthesizable hardware code, verification may use the different functions of the different languages, resulting in generation of a lot of simulation techniques and methods which can be chosed as needed. In order to reduce the time and cost in product development, it is not enough to only improve the design abilities of chip design companies. How to establish the verification strategy and techniques, program the time table, and choose the verification languages, along with their EDA support tools also come to be a big issue.In this paper, the denoise module algorithm are analyzed and researched to some extent. In addition, through studying the popular verification techniques in IC industry, the whole functional verification for NSR module in TD-SCDMA/GSM chip SC6800E is completed, with the use of advanced verification methodology and the support of EDA tools. The verification environment platform in the chip level for NSR is also detailed in this paper. This is a multi-language simulation environment using Verilog, Systemverilog, etc. The bus function is implemented by using the reusable BFM (Bus Functional Model), so that the verification work can carry out at the higher level more efficiently.Also, in this paper, there are enough test cases designed for NSR module verification, which aim at covering all the features of the design. The verification platform is described using Systemverilog, and perl script is used to control the whole simulation in the verification structure, so that reference model in c_model can be called on the fly, the input parameters can be generated randomly and the output data can compared with the expected data automatically. The author also developed an interrupt process routine using Systemverilog, which can be used by several modules including NSR. So the interrupt signal detection can now rise to chip level, which means you need to detect the interrupt signal which has been processed by ARM. Besides, with the other verification engineers' team work, a simulation platform for image signal processing system has been built up. This platform implemented the system level verification of all ISP modules. Moreover, the verification of NSR module is also implemented with FPGA verification as an effective supplementary of simulation-based verification. After the design of netlist, post-layout simulation is also done, which is the last sign-off step before taping the chip out for chip design department.With the support of advanced EDA tools and chip level verification environment, in this paper, the code coverage analysis and statistic job for NSR module are also done. The NSR module verification has passed the quality review flow for module verification in Spreadtrum Communications, Inc. All those indicate that the verification method and structure described in this paper are highly flexible, efficient, and reusable, thereby suitable for application in SC6800E chip project development.