Automated FPGA design, verification and layout

The design and layout of Field-Programmable Gate Arrays (FPGAs) is a time-consuming process that is currently performed manually. This work investigates two issues faced when automating this task. First, an accurate comparison of layout area between manually and automatically-generated layouts is performed. For the single commercial architecture considered, this work found that the area of an automatically-generated layout is only 36% larger than that needed for a manual layout. The second half of this work focused on the steps needed to implement a complete FPGA using automatic layout tools. New tools that aid the design and verification of an FPGA are presented and an FPGA created with those tools was verified in simulation and then sent for fabrication. This indicates that automatic layout tools can be used to design complete FPGAs in a fraction of the time required for manual design.