The Research Of Partially Depleted SOI CMOS Devices And Design Of SRAM

Silicon-on-Insulator (SOI) CMOS technology is becoming another mainstream technology for VLSI. Owing to its inherited characteristics, SOI CMOS technology is especially capable of providing deep-submicron VLSI devices for next-generation high-speed, low-power, system applications using a low-power supply voltage. Since the cost to produce SOI materials was high in the past, the application of SOI materials was limited in military industry and aerospace. More recently, the advent of new SOI wafer fabrication techniques and the explosive growth of portable microelectronic devices have attracted considerable attention on SOI for the fabrication of low-power, low-voltage, and high-frequency CMOS circuits.In this thesis, we study the electrical characterization on SOI wafers and design a SOI SRAM structure.The electrical parameters of buried oxide and interface state in SOI structures influence the performance, reliability and radiation hardness of devices fabricated in the superficial silicon film. Based on the experimental results and theory analysis, electrical characteristics of SOI devices were discussed, especially floating body effect. Due to the buried oxide structure, floating body effects of PD SOI MOS devices are important in determining their behavior. Back gate bias, kink effect and transient effect caused by the floating body, may bring in bad influences to circuits made of PD SOI devices.Because of the small junction capacitance, the small substrate bias effect and radiation-hardness of SOI devices, we design a SOI SRAM structure and study the performance of our circuits. The results we got in the simulation and test are valuable.In order to resolve the floating body effect problems, body contact has been used. We present various techniques, including Schottky body contact, Ge-implanted source/drain techniques, argon-implant technique, and so on.