0.13 Micron SOI CMOS Commercial Process Development

Because of SOI transistor has certain obvious advantage over counterpart bulk transistor, SOI is always one of the focuses of research and development. This thesis describes the development of0.13um SOI CMOS process platform, in a commercial large volume IC manufacturing line. This project finishes the0.13um SOI CMOS process development from scratch.There is no other SOI process in the company as base of this project. So the0.13um SOI CMOS process development takes0.13um bulk CMOS process as foundation, to start the development. This thesis emphasizes differences between0.13um SOI and bulk process, describes and analyzes the differences. In the development, we encounter the problems or face the choices of SOI top Si thickness and STI depth, active area Si film bending up, gate polycrystalline Si film thickness optimization and source/drain implant doping penetration of gate, etc. This thesis describes and analyzes these problems, and work out solutions.This0.13um SOI CMOS process uses top100nm top Si SOI wafer, and STI bottom touches top surface of BOX. Hence, transistors are fully isolation by dielectric material, instead of N/P Well diode isolation. Because of the thin top Si thickness, this0.13um SOI CMOS process is grouped into thin film SOI process. Transistors of this process are partially depleted transistors.The choice of thin film SOI process brings the problem of active area top Si bending up problem. Based on experiments, we work out the solution that, replace furnace liner OX by RTO liner OX. RTO OX thickness is pretty thin, about20~30A, we add another CVD OX film, the thickness is150A, as a buffer layer for STI HDP DEP process. The active area top Si bending up problem is effectively suppressed.Top Si thickness of this process is thin, hence source drain implant depth is low as well. To keep gate polycrystalline Si film properly doped, gate polycrystalline Si film is chosen as130nm, thinner than0.13um bulk process. In development of the process, we encountered source/drain implant doping penetration of gate problem. Source drain implant energy is lowered from30Kev to25Kev. Based on experiment, this is the optimized implant energy, to get source/drain implant doping to touch BOX surface, and gate polycrystalline Si film properly doped at same time.0.13um SOI floating body transistor, shows kink effect in ID/VD curve saturation area. The kink effect is caused by impact ionization at drain high electrical field, electron goes to drain, hole accumulates in floating body, hence charge up body area, Vt decreases, ID increases, kink effect shows up.In3.3V body contact SOI transistor ID/VD curves saturation area, we can see kink effect as well. The reason is that T-gate body contact has a high body sheet resistance, and body is connected to ground through a high resistance, makes the body contact is not effective enough, shows up partial transistor floating body effect.We can see ID goes lower when VD goes higher, in3.3V body contact SOI transistor ID/VD curves. This phenomenon is induced by SOI transistor self heating, which is caused by lower thermal conductivity of BOX. Self heating phenomenon is not obvious in1.2V NMOS ID/VD curves, because1.2V NMOS generates less heat, and this process SOI wafer BOX is pretty thin, only150nm.Compared to0.13um bulk NMOS, this SOI process1.2V body contact NMOS shows no advantage for leakage current. This0.13um SOI process is a generic technology, not low leakage technology. Transistor’s leakage current is dominated by channel sub-threshold leakage current. The lower junction leakage advantage of SOI transistor does not contribute too much to transistor total leakage current. Differences between0.13um SOI process and counterpart0.13um bulk process, such as gate oxide, source/drain, well, thermal budget, STI, etc, makes SOI NMOS channel sub-threshold leakage current is higher than its counterpart’s.We observed linear kink effect in SOI1.2V floating body NMOS. This is caused by GOX tunneling current, since the GOX thickness is low, only18A. When drain voltage is low, gate voltage is high, noticeable GOX tunneling current occurs, and holes of the tunneling current accumulate in floating body of NMOS, shows up linear kink effect, and2peaks can be seen on the Gm curve.Through experiments and research, problems are solved and various phenomena which are unique on SOI transistors are analyzed, process development is done. This project set a foundation of smaller technology node SOI process development, or other SOI processes on same technology node.