Design And Implementation Of Code-POCSAG Encoder Based On SOPC

This subject stems from the item, radio-paging comprehensive experiment, ofcommunication exercitation system, which is one of the experimental items for the studentsmajor in communication. This item contains three parts, connection of computer, pagingstation and antenna, application of paging software and operation of compiling and sendingmessages. The precondition of this subject is the implemented tradition encoder circuit ofcode POCSAG. And the purpose is to promote this implemented design, integrating theexperiment modules into one FPGA chip to reduce the amount of chips and improve theability of programmable and upgradeable. In the module top-down design method isimplemented to design the hardware description language, and each module is integrated intoone FPGA chip. The task of this subject is to reconstruct the code POCSAG encoder.This dissertation describes the code format of code POCSAG and the implementation ofthe encoder based on SOPC. Alone with the development of programmable logic device, thesoft-core of microprocessor can be embedded into the programmable logic device. SOPC isnot only highly flexible but also programmable, which makes it as the developing trend ofmodern electronic technology and system. This dissertation adopts the 32-bit microprocessorsoft-core NiosⅡand programmable chip Cyclone supplied by the company Altera, and takesthe SOPC exploring suite Quartus and NiosⅡIDE of Altera as design tools. The main part ofthe whole system is FPGA and its expander. System design includes hardware design andsoftware design. Hardware design is accomplished by VHDL language. Software design isaccomplished by C language. The compile and debug of the program is achieved at last, andthe SOPC design of code POCSAG encoder is realized based on the Cyclone chip. Bydetection, the POCSAG encoder of this design has stable performance, and achieving thedesign requirement completely.