| Since the appearance of kinds of high-performance digital signal processor, it becomes hot in embeded system development that real-time,high-speed dealing the huge-data digital video/audio encoding,decoding and other media applications with a embeded system with a digital signal processor. This paper researches the design and implemention of the video display subsystem based on YHFT-DSP, implementing two solution.The first solution is that the video display subsystem is implemented based on YHFT-D4B and FPGA. In this subsystem, the decode program is running on the YHFT-D4B, and FPGA scales the images of video,changes the scan method, formats the image data to video streams. Now the debugging of system on board has been finished. The system has a good interface compatibility and a steady performance. It can continuously provide a channel BT.656 streams. Then this paper analyzes the limitation of the first solution, and provides the second solution after researching lots of document of current digital media processor.The second solution is to design a new digital media processor, YHFT-VDSP, including a advanced YHFT-D4B DSP core, a video capture subsystem, a video display subsystem and a hign-speed outside memory interface. This paper implements the integrated video display subsystem. Video display subsystem includes a asynchronous FIFO module, a pipelining video filter module and a programable format output module. This paper has completed the Verilog codes and it has done a simulation. The result shows that the performance of the second solution is better than the first solution, and the second solution can make up the limitation of the first solution, supporting SD and HD display equipmentAt the end of this paper, we discussed the verification of the integrated video display subsystem in the YHFT-VDSP, including simulation and FPGA emulation. A method, using a YHFT-D4B and FPGA system, is provided to simulate the interface timing of video display subsystem, for FPGA emulation. |
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