Design And Application Of DDR SDRAM Controller

Memory is one of the crucial devices in the digital system at present,the DDR(Double Data Rate) SDRAM has many advantages for it's large capacity and high speed,it has been used in quite a number of fields,such as the Server,the WorkStation,and the Personal computer. The pivotal technologies of DDR SDRAM and memory controller such as Structure,Interface and Timing are explored in this article,after a research on the main feature inside the DDR controller,several functional modules of the controller are designed out,and implemented via Altera FPGA and IPcore.Additionally,the performance of the DDR controller is simulated and tested by simulation tool soft.TOE(TCP Offload Engine) network interface card can accelerate the TCP process. A practical application with the DDR controller is introduced in this article, it will be used in a TOE network interface card(TNIC) and make the DDR SDRAM a high speed data buffer,in this card,a TCP preprocess module and a postprocess module along with a IP process module need to access DDR SDRAM via the controller,this article also describes a DDR controller bus arbiter which makes many function module can access DDR memory efficiently in course of the TOE NIC design via FPGA. the DDR controller becomes a vital component of the entire TOE system. This article put emphasis on discuss the design process and the implement methods about the arbiter,and besides,the performance of the controller and the arbiter has been analysed, several parameters which affect the performance also have been deduce,some valuable conclusions are gained.Finally,about the boards'design in the engineering process,some skills of the traces and placement of the signals between controller and the DIMM(Dual In-line Memory Module) socket are analysised in particular. In addition,DDR chip's power consumption and the signal's timing margin have been discussed.