The Design And Implementaion Of Shared Memory For Multi-core DSP

Digital Signal Processor(DSP)is an embedded microprocessor that realizes real-time processing of digital signals.The increasing demand for high-performance embedded computing performance puts forward higher requirements for DSP performance.As the semiconductor technology is reaching its limit,multi-core architecture is becoming a main development direction to improve DSP performance.However,the increased computing performance due to the muti-cores is constrained by the memory access performance of the hierarchical multi-core shared Cache structure,which affects the performance of the multi-core DSP.In response to this problem,the on-chip shared memory based on Scratch Pad Memory(SPM)without access miss and data consistency overheads has gradually become more advantage in real-time digital signal processing.M-XDSP is a self-developed multi-core digital signal processor for image and radar signal processing.Based on the M-XDSP architecture and design requirements,this article carries out the design and verification of the shared memory of M-XDSP,and realizes the parallel data access to shared memory on-chip for each host.The main work and innovations of this article are mainly reflected in the following aspects:1.According to the M-XDSP on-chip network interface protocol,the shared memory based on the SPM structure is designed.And the parameterized design of the memory capacity and parallel memory access bandwidth is realized,so that the Shared memory can meet the different application.A full access pipeline to supports ECC has been designed.A error correction code module to support small-grained writing is embedded in the memory access pipeline realizes a 256-bit error correction function,which improve the reliability of shared memory data access with a lower hardware cost.2.For multiple parallel memory access requests,an arbitration strategy with a configurable priority threshold is proposed,which implements a parallel memory access arbitrator that dynamically adjusts the priority of multi-port access,which not only effectively prevents a single memory access port from the phenomenon of "starvation" and "full",but also enhances the priority configurable flexiblility of multi-core parallel memory access performance.3.A module-level verification platform based on SV was built,and the functional verification and performance evaluation of Shared memory were completed.The verification results show that the Shared memory function is correct,the code coverage rate reaches 99.83%,Based on the 28 nm process of a certain manufacturer,SM logic synthesis is completed under the 1.33 ns clock constraint;the timing meets the requirements.Finally,we write regular memory access test cases with different memory access steps to evaluate the memory access performance of Shared memory.The results show that the bandwidth efficiency of Shared memory will not be affected in the case of continuous steps of small-grained writes,and the increase in the number of ports is beneficial to the bandwidth of Shared memory is developed.