Design Of External Memory Interface In Reconfigurable System For Communication Application

Reconfigurable computing technology has been involved in many high-performance computing areas,such as media processing,wireless communications,bio-information,numerical weather,molecular simulation and so on.Reconfigurable computing technology has become an important development direction of future high-performance computing architecture.However,when the reconfigurable technology is applied to the applications with high parallelism and high performance requirements such as media processing,wireless communication and so on,the calculation process contains a lot of data access,and the delay of data access has become a computational performance bottleneck.So the optimal design to reduce the data access delay and improve the system performance is more and more important.A memory access interface module is proposed to reduce the delay of data access and improve the system performance.Based on a coarse-grained reconfigurable system used for wireless communication applications,this thesis focuses on reducing the delay of data access.Firstly,the signal processing of the wireless communication receiver is analyzed,and the three kind of features of the data access about kernel algorithms are extracted.Secondly,high-speed access protocol is proposed to reduce the delay of data transmission based on the three kind of features of the data access.Thirdly,a data cache is designed to improve the system performance based on the coarse-grained reconfigurable system.Fourthly,a new prefetching mechanism is proposed to reduce the hit miss rate of the cache according to the features of the data access.The register transfer level function verification based on the coarse-grained reconfigurable system is implemented.And the performance verification is implemented based on the chip board.The proposed prefetching mechanism achieves a performance gain of up to 8.11%with the 8-way,64-Byte,128-KByte data Cache.External memory access interface achieves a performance gain of up to 15.36%compare with the traditional design on the same coarse-grained reconfigurable system.