Design Of The Data Cache SRAMS

In a modern microprocessor, Cache has become an absolutely necessary function component. Its speed, reliability and power have been the main criterions to evaluate the performance of a microprocessor. It has an increasing requirement on microprocessor performance because of the extensive applications. But it is still a difficult problem to design a high-speed and low-power microprocessor.On the basis of deep researches on the data Cache working mechanism and the static random access memories (SRAMs) technology, we design the SRAM data module of the Cache, based on the 0.18μm standard processes. The performance ofSRAM data module has great effect on the overall performance of the Cache.The main contents of this paper are as follows: Firstly, researches and designs of the structure of the SRAM partitioning and the memory array. Secondly, researches and designs of the encoder, sense amplifier, pre-charging circuit and write controller. Thirdly, optimized layout designs in order to suppress noise, reduce delay, re-use module and compact structure. Fourthly, optimized circuit designs to cancel the unnecessary write and read operations in order to save power consumption. These unnecessary operations include unnecessary amplifying power consumption during reading and bit-line driving power consumption during writing.In the normal temperature, the layout simulation results show that the write-time of SRAMs is less than 1.0ns, and the read-time less than 1.3ns at 300MHz. Our designs have been implemented in the data cache of the X microprocessor successfully. The testing results of the real fabricated chips show that our designs can completely meet the requirements.