Research On Turbo Decoding Algorithm And FPGA Implementation

In communication systems, people consistently devote themselves to research on efficiency and reliability of data transmission, channel error correction coding technology is always the emphasis of the research. Since Turbo code was proposed in 1993, it has received great attention and become a research hot spot due to it's near Shannon limited good coding performance. After more than ten years' research and development, Turbo code has begun to apply in the real communication systems. Now, how to implement the Turbo encoder and decoder with hardware effectively has become a research hot spot.In order to implement the Turbo decoder based on FPGA, firstly, this thesis has analyzed the fundaments of turbo code and the 3GPP Turbo encoder and internal interleave algorithm. Secondly, this thesis has carried on detailed theory analysis and computes complexity comparison of MAP algorithm, Log-MAP algorithm and Max-Log-MAP algorithm, and has also analyzed the major factors affecting the Turbo coding performance with MATLAB simulations.Based on intensive analysis of three decoding algorithms, this thesis has adopted Max-Log-MAP decoding algorithm to carry on the design and implementation of Turbo code based on FPGA. Data quantization, fixed-point presentation, the FPGA design of key compute modules in Max-Log-MAP sub-decoder and internal interleaver in Turbo decoder of 3GPP standard have been discussed. Finally, a fixed decoding length Turbo decoder based on FPGA has been designed, and function timing verification and FPGA fixed-point simulation has been separately carried on with ModelSim and MATLAB.