Design Of Low-Power Dissipation SoC Based On Leon3 Processor

Power dissipation has become the main concern in the design of IC after speed, area and DFT(design for test).The thesis accomplished the design of clock-gating circuit and bus with Zero-Transition function,optimized the power of SoC based on Ieon3 processorIn modern IC design, the power of bus can be up to 60% of the entire power of SoC. The first choice of IC designer is to optimize the power of bus. The thesis has accomplished the Zero-transition encoder and decoder with VHDL. It reduced the power by coding the transmitted data for minimum switching activity. The result shows that when 5000 continuous addresses are visited, the entire dynamic power of system reduce by 11.29% compared with the designs which don't use TO encoding.In addition, the power can be optimized further by clock-gating. The thesis introduced the characteristics of clock-gating technique and clock-gating's influence on synthesis and timing analysis. The circuit with clock-gatings has been designed with Synopsys' Design Compiler. The result shows that the entire dynamic power of SoC reduces by 15.5% compared with the design which don't use clock-gating.The thesis analyzes the entire power with Design Compiler and PrimeTime.The entire power of SoC reduce by 25.22%. It has abundant guide significance of theory and practice.