Design And Analysis Of CMOS Integration CPPLL

Phase-locked loop(PLL) is an important module in analog and mixed-signal circuit, it can track input signal's phase and frequency, then it outputs locked -phase, small jitter signal. In system application, it can be used in lots of field, such as communication, numerical electric circuit and wireless system.Charge-pump Phase-locked Loop(CPPLL) is a kind of PLLs, its advantage is that it can be proved its static error is zero in theory, it can be proved it has lots of Characteristics in practice, such as high speeding, low power, low jitter, and so on.. It is a simple and high-efficiency method to design PLL. Althrough the CPPLL's theory is comparative perfect, in the process of designing CPPLL, it includes in many ways, for example signal and system, integrated electronics, layout, semiconductor process and test. So it is difficult. Because of this, it is essential to thoroughly research the CPPLL, master the CPPLL's design rule and analysis method.This thesis design a CPPLL for a 14-bit high speed digital-analog conversion, the CPPLL supplies all the clock signals of the DAC system, its reference clock frequency is from 3MHz to 160MHz. The thesis starts with the development of CPPLL. deduces the basic theory, and all kinds of parameters, such as dynamic performance, track characteristic, capture time, high order loop and phase noise. On this base, this thesis presents the specific design blue prints of CPPLL, simulation schemes and the analysis results of every modules, for example the phase-frequency detector without dead zone, charge-pump without charge-sharing and clock feed through, third-order filter for removing the ripple, six-stage differential oscillator, prescaler and clock distribution. In the end, Because of the analog circuit's complication, the thesis summaries the principles of the PLL design layout.The design used the model of SMIC 0.35 mixed-signal process, its power supply is 3.3V, the simulating tools are cadence's Spectre, Hspice and Synopsis's Nanosim. The simulation result is proved that the CPPLL satisfies the design request. Its locked time is greater than 0.090ms, and smaller than 1.162ms. When the reference clock is 100MHz, VCO frequency is 400MHz, its Jitter (root-mean-square) is 134.83ps, and amount to phase noise is -62.8dBc@1MHz.