The Digit Integrated Circuit Design Of The Passive Electron Tag Based On The Protocol Of ISO/IEC 14443-A

Because of the excellence in large memory capability, high security level and contactless read-write, the technology of radio frequency identify (RFID) has gotten a broad application. Among all the protocols that suitable to the RFID, the protocol of ISO/IEC 14443-A suitable to frequency 13.56MHz is the mainstream of the market. This paper researches and designs the passive electron tag based on this protocol, including the channel safety unit, the information safety unit and the controller unit. Based on completing the content of the protocol, This paper designs the optimizing project of the DES cipher system, at the meantime, the communication project, to read and write the stored data, and its verification project are designed.Firstly, this paper introduces the digital circuit system structure of the passive electron tag, the safety question and the parameter that the protocol of ISO/IEC 14443-A requests. Secondly, this paper labors the channel safety technology and the information safety technology that the digital circuit system is involved, especially the optimizing project of DES cipher system of the information safety technology. Also, the communication and verification project of the digital circuit system are brought forward. Next, this paper specifies the method of designing the digital circuit system and verifies its operating result. At last, the great production of this paper is summarized and the ameliorating direction in the future is pointed out.This paper established the circuit for each module in the above units of the digital circuit system, including the data code and decode module, the channel code and decode module, anti-collision module, authentication module, the encrypt and de-encrypt module, the master and slave controller module. Then, the digital circuit system was verified in the NC-Verilog emulator. The result shows that the digital circuit system was in accordance with the expected functional request of the verification. Next, the digital circuit system was synthesized by the Synplify Pro tool with EPF10K100GC503-3 CMOS chip of the Altera as the target device. The synthesized circuit was verified in the Maxplus2 emulator, and the result showed that the digital circuit system was in accordance with the expected timing request of the verification. At last, the digital circuit system was synthesized by the Design Analyzer tool of the Synopsys with the 0.35μm technology of Semiconductor Manufacturing International Corporation (SMIC), the chip area was 36877.75μm~2 and the power was 30.8458mW. At the meantime, basing on the synthesized netting table, the layout of the digital circuit system was generated by the Silicon Ensemble tool of the Cadence and the digital circuit system is being tape-out.The digital circuit system of the passive electron tag this paper designs gets a good optimization among the speed, area and power. The result showed that it can satisfy the technology index the protocol of ISO/IEC14443-A requests the passive electron tag.