The Design Of DDR3Memory Interface Based On MPSoC

With the development of technology based on MPSoC, multi-core processor hardware design scale and complexity continues to increase. the peripheral interface requirements are more and more abundant, the system architect must solve some complex problems in high performance systems, including system structure,algorithm and function range. In general, a basic problem of these applications is memory, with the increase of MPSoC computing system data bandwidth, and enhance the processing ability of the processor, but also to improve the storage capacity, data bandwidth and access delay requirements.Based on architecture of the MPSoC, the memory bandwidth and data transmission efficiency problem becomes the key problem of new.This paper first introduces the architecture and function of a hierarchical heterogeneous multi-core processor chip which is designed by the author’s research group. The chip uses the NoC communication structure, Processor and a variety of IP core communicate with the network through the resources interface. In order to guarantee the efficient data processing unit and the memory of exchange, the multi-core processing chip external memory components using a new generation of DDR3SDRAM. DDR3SDRAM memory can save power consumption of the system, improve the system performance and achieve maximum throughput. Paper presents the hardware architecture of the multi-core processor and its characteristics, process focuses on the design and verification of DDR3memory interface.In the DDR3memory interface design, the author using Xilinx latest MIG high-speed memory interface solution that allows the user through the user interface to quickly establish the connection from the FPGA internal control logic to the external memory in Virtex-6devices.The author designs the user interface module-DDR3NI module of DDR3memory interface IP core, the module’s main role is that convert the PCC signal which from NoC router network into user interface signal of DDR3memory IP core, in order to have two protocol conversion. paper finally introduce a set of Flash programming verification platform with which the project team conducting the design of hardware and software co-verification and the Flash programmer platform is used to the actual verification of DDR3memory controller on board-level verification.The results of the validation DDR3memory design is working correctly and has the characteristics of high efficiency, high bandwidth.