Design Of 8-bit MCU IP Core And Research On FPGA Verification

IP core reuse technology is the technical core of SOC design. It leads to simple chip design, short time to market, as well as less failure risk. 8-bit MCU IP core is one of the most popular embedded cores in SOC design.SDU_M08 MCU IP core uses Harvard architecture and employs an instruction set which is fully compatible with Microchip's PIC16C57. It can be widely used in the field of industrial control, automobile, instrumentation, and appliance and so on.Based on careful analysis of system architechture, instruction set and system time sequence of PIC16C57, the thesis gives a description of system partition and RTL coding of each module. The core is partitioned into two parts which are control units and datapath units. All modules are elaborately designed and some are specially optimized. Synopsys' DesignWare library is used for critical path improvement and timing optimization. The datapath model makes design of datapath fast and simple; ALU is optimized using operand isolation technique for power reduction. Four-level read scheme is adopted for General Purpose Register design in order to reduce the fan-out of the data bus.As to verification, much research is focused on FPGA prototype technology. After making a detailed verification strategy, FPGA verifation platform is built. FPGA on the platform is also used to program the flash rom, solving the problem of on-line configuration. After building the FPGA platform, simulation, logic synthesis, Place & Route are performed to complete the FPGA prototype. For FPGA testing, boundary scan test technology is used.During the design and verification, many EDA tools are used, including Altium's Protel DXP, Synopsys' VCS and Design Compiler, Mentor Graphics' Modelsim, Synplicity's Synplify Pro and Altera's Quartus II.The research of this thesis would necessarily contribute to the development of more complex MCU IP cores.