Design Of Boundary-scan Controller Based On FPGA

With the printed circuit board functions and structures gradually complicated, systems connections between the various functional units spacing more detailed, the traditional method based probe testing method has been very difficult to meet the needs of the present test. Boundary scan test (BST) technology through places the boundary scan register unit on integrated circuit interior each pin, was equal with the hypothesized probe head which has exerted the drive and observed the response, might enhance the system's observability and controllability through this technology and reduce the test difficulty. This article designed the boundary scan controller based on FPGA for such test demands.A complete boundary-scan test system mainly contained the test part and target device, including test pattern, data generation and boundary-scan controller of the test part. The boundary-scan controller was the core of the system, it was mainly to achieve the automatic conversion of JTAG protocol and then brought about the boundary scan test bus signals to meet the IEEE standard. Boundary scan test system's performance mainly depended on the efficiency of boundary-scan controller. Therefore, to design a boundary-scan controller which can complete converting JTAG protocol accurately and fast was the major task of this research paper.Firstly, this article introduced the basic principles of boundary-scan technology, analyzed the physical basis of boundary-scan test, instructions and relevant standards with design for testability, then proposed the overall design program of this boundary-scan controller. Secondly, this article adopted modular design thinking, VHDL language description to complete the boundary-scan controller hardware design. Then, authenticated the functional modules based test bench making use of top-down methodology, integrated boundary-scan controller into the SOPC to form-based SOPC boundary scan test system using of embedded system design thinking. This article made use of the software and hardware co-simulation on the SOPC system to realize the functional verification of boundary-scan controller. Finally, tested the hardware and software of the whole system with the feasibility on the basis of Signal Tap II hardware debugging. This article has achieved the desired design goals from the test results, the boundary-scan controller design is correct and feasible.This article designs the boundary scan controller which has the proprietary intellectual property rights and may with other processor union to constitute a complete boundary scan test system, and provides a module with a great deal of use value, which has very obvious practical significance.