Design And Verification Of Interface Circuit Of Embedded FPGA In Reconfigurable SoC

System on chip is a dedicated device.Its research of generalization has been an important topic in the microelectronics industry.Among them,reconfigurable SoC technology is an important way to achieve general-purpose SoC.In this type of SoC,there is at least one reconfigurable unit.According to the specific application,the user can compile the part of the chip and make the online upgrade more efficient.The reconfigurable SoC has both the advantages of microprocessor and programmable devices,this makes it has higher flexibility and greater ability to divide hardware and software than dedicated SoC.Therefore,the research work of combining reconfigurable technology with dedicated SoC has gradually become a hot research direction of the microelectronics industry.Based on the project of multi-bus reconfigurable processor chip,this thesis first introduced the foundation of reconfigurable technology and related research work,and described the advantages of reconfigurable SoC and its design concept,and leads to the definition of embedded FPGA's reconfigurable SoC.Then the thesis analyzes the working mode of the embedded FPGA's configuration interface circuit.Based on the traditional PROM loading method,the thesis proposes the loading method based on the processor control,which makes the loading configuration of FPGA more flexible and more convenient.In addition,this thesis calculated the time to download the configuration file to FPGA in two ways,the results show that two kinds of loading methods can meet the requirements of the technical indicators that are less than 100 ms.As the FPGA core needs to be attached to the bus,in order to solve the timing issues of CPU access FPGA,the thesis designed the bus interface to make user easy to use.The interface generates the FPGA's access clock by dividing the bus clock,and can provide synchronization;asynchronous and asynchronous delay's access timing.In order to meet the timing of various resources,the interface also sets four space of chip selections,each space can be programmed independently.Finally this thesis used the Verilog language to complete the verification platform in theLinux system environment,and used the NCsim simulation tool to verify the function of the interface circuit.The specific work includes the design of the verification component,the verification of the functional verification,the verification of the use case,the analysis and summary of the verification results.The result shows that the two load modes of configuration interface circuit can work normally and the different access modes of the bus interface circuit can be accessed correctly.Through the design and verification of the interface module,the thesis achieves the flexible configuration and universal access function of the FPGA core,makes the chip function more perfect.It can be used as reference for the design of reconfigurable chips.