Analysis And Design Of Electromagnetic Interference Suppression In The Substrate Of CMOS RF Integrated Circuit

With the rapid development of wireless communication,its core devices such as the radio frequency integrated circuits(RFICs)are moving towards high performance,high integration but low power consumption.The technical trend shows that the RFICs is gradually integrated into CMOS Systems-on-chips(SoCs).As a consequence,the highly integrated RF SoC integrates digital circuits that generate a lot of substrate noise,which will seriously affect the performance of the RF circuits.Therefore,the elimination of the electromagnetic noise of CMOS substrate is of vital important for RFIC design.This research is to develop the novel modeling and design techniques to eliminate the substrate electromagnetic interference(EMI)problems of RFICs,the innovative solutions obtained are summarized as follows.First of all,to analytically and experimentally verify the susceptibility to the substrate noise for existing RFICs,the effects of substrate noise on the frequency modulation of a CMOS voltage-controlled oscillator(VCO)circuit output signal is analyzed and verified.In addition,the simulation of doping concentration on the CMOS lightly doped substrate is carried out.The three-dimensional full-wave simulation and the analysis of electromagnetic performance of the guard ring structure based on this substrate are performed.Based on these analyses,the effect of different geometrical parameters and material parameters on the isolation of the guard ring is concluded,which provides basis for the IC designers to select suitable parameters to improve the performance of guard rings.Secondly,in this research,a set of accurate and uniform equivalent circuit modeling method for guard ring based on CMOS lightly doped substrate are proposed,which are suitable for the P+/N+ guard rings and the "structures without guard ring".The equivalent circuits use analytical formulas to determine the lumped component values,accurately calculating the impedance of the guard ring structure.The model is suitable for a wide frequency range and can meet the high frequency requirements of RF circuits.Based on the proposed model and the results of the guard ring performance,the design guides rule for guard rings based on CMOS lightly doped substrate is developed.This guideline can be used to optimize various guard rings,and conduct the tradeoff between the isolation and the area size,thereby minimizing the chip area and reducing costs.Furthermore,to enhance the limited isolation performance of the conventional guard rings,a diode-based guard ring based on CMOS lightly doped substrate is proposed and implemented.In this structure,the p-n junction capacitance in the guard ring resonates with the inductive interconnect to the ground,forming a very low impedance path for the substrate noise current,which results in better isolation than the conventional guard rings.Compared with the conventional P+ guard ring,the isolation of the proposed guard ring can be increased by up to 30 dB at the resonant frequency.In addition,an equivalent circuit using lumped elements suitable for the proposed guard ring is developed.The circuit is applicable to various geometrical parameters and material parameters of the structure within a certain range.Based on these models using lumped circuit,the impedance of the structure is analyzed and the mechanism affecting the resonant frequency of the structure is investigated,which makes it possible to design a diode-based guard ring in the expected operating frequency range.Finally,to reduce testing area size for the S-parameter measurement of large-scale guard ring structures,an array-based measurement method for measuring S-parameters of on-chip devices is developed in this research.The array-based method uses several key technologies such as transmit/receive(T/R)switches,de-embedding method and RF-oriented layout pattern,and a good balance between the measurement accuracy,chip area,and operating frequency range is obtained.The designed test chip using a commercial 0.13-?m CMOS technology contains a variety of array-based circuits that verify the effectiveness of the array-based method for S-parameter measurements in the GHz range.Compared with conventional measurement methods,the array-based measurement method can save about half of the area with acceptable accuracy.