Design And Implementation Of Communication Protocol Controller In Communication Processor SoC

Based on the national defense pre-research project "Research on the key technologies in Designing for Communication Processor SoC", communication protocol controllers are researched in this thesis.Firstly, as the architecture of MOTO's communication processor, PowerQUICC is introduced, especially the architecture and features of Communication Processor Module (CPM) as well as its sub-modules including CP, DPRAM and FCC.CPM supports many kinds of communication protocols. The objects researched in the thesis are controllers which support ATM and HDLC. The thesis introduces these two protocols in order to make the design of these two controllers easily understood.On the basis of the introduction above, the principles and the design of the ATM and HDLC controllers are researched, mainly including the processes of data transmitting and receiving and the memory used by them. For the ATM controller, the thesis also emphases on the design of the VPI/VCI address lookup mechanism when a cell is received, and the APC unit which is in charge of the flow control when transmitting the cells with different traffic types. The flow charts are given to describe the processes of transmitting and receiving an AAL5 cell.After researching on the working process of the HDLC controller and the relative memory, the thesis puts forwards the implementation of the HDLC controller. In this implementation, the architecture of transmitter and receiver of FCC are designed according to the functional requirement of HDLC controller, as well as the working process and the functions of the sub-modules.Finally, we implement the design of FCC in HDLC controller mode with Verilog HDL, and make functional simulation using the software ModelSim to testify whether it satisfies the functional requirement with all different kinds of input.