Design Multi-Processor System Based On Network-on-Chip Architecture

With the IC progress of manufacturing process technology, packaging and testing technology and design methodology, the size of transistors are smaller and smaller, chip designers can use the transistors more and more in the chip. Thus, it can accommodate more circuit with the progress of VLSI design, there will be more IP core integrated on the same SoC chip, multi-core processor systems (MPSoC) has become the development trend of the future embedded in the field. But when hundreds of IP core integrated on a single chip, the traditional bus encountered difficulty, which is about Global clock synchronization in the design. Address space is limited and can not support multi-node parallel access and so on. In order to solve these problems, it is proposed for a brand-new bus architecture NoC. The mainly idea of NoC, the computer network technology are transplanted to the chip design, which is to solve the multi-core processor system for the interconnection between communication. It is completely resolved from the architecture of communication bottlenecks, it see packet switching as a basic communications technology, using global asynchronous and local synchronous for the communication mechanism. Against this background, this paper analyzed related technology of NoC, proposed a framework of network-on-chip based on the 2D Mesh network topology and designed some modules such as switch nod, resource net interface, bus arbiter, serial port and realized XY routing algorithm. What's more, according to ATA/ATAPI-6 agreement and 802.3 agreement, the paper designed Hard Disk controller and MAC controller. At last, the paper builded a MPSoC with the architecture based on NoC and peripherals such as HDD controller, MAC controller, and this architecture has been verified on Xilinx XUP Virtex-II Pro broad which is promoted by Xilinx company.