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The Design Of Serial Communication Controller Based On PCI Bus

Posted on:2017-12-07Degree:MasterType:Thesis
Country:ChinaCandidate:Q P GuFull Text:PDF
GTID:2348330491964305Subject:Integrated circuit engineering
Abstract/Summary:PDF Full Text Request
With the Internet entering the era of big data, research on high speed serial communication has become an inevitable trend. The network interface card of the router is controlled by the high speed serial communication controller based on Component Interconnect Peripheral (PCI) bus. High level data link control (HDLC) is the protocol most commonly used in the data link layer, it has powerful error detection capability and high reliable, efficient, transparent transmission characteristics and can be used in any high-speed data transmission system oriented to bit. Therefore, in this thesis, the HDLC protocol controller is used to deal with the data in the serial communication to ensure the correct transmission of the data.In this thesis, a serial communication controller based on PCI bus is designed by the analysis of PCI bus and HDLC protocol, and the interface signal of HDLC controller and PCI bus is described. The design is divided into the send module and the receive module. The work of the two modules do not interfere with each other because they each have a controller. HDLC transmitter includes parallel to serial shift register, frame check sequence (FCS) generator, zero insertion, the generation of the flag and abort word and transmission control module. HDLC receiver includes the detection of the flag and abort word, detection of zero, FCS checker, and the control module. Among them, the FCS checker uses the cyclic redundancy check (CRC) in order to ensure the correct and integrity of data transmission. By focusing on sending and receiving control module, the thesis explains the process of data sending and receiving in the system in detail.Verilog HDL language is used in this thesis to design the circuit, and the Modelsim software is used to carry on the function simulation. Under the TSMC90nm technique, the operating frequency of the circuit can reach 400MHz. Finally, the verification of FPGA proves that the design is able to complete the function of sending and receiving data correctly. In addition, if a byte of data is sent by the use of 16 bit CRC, the transmission module's maximum throughput can reach 80Mb/s and the maximum throughput of the receiving module is up to 94Mb/s, which can meet the need of high speed serial communication.
Keywords/Search Tags:HDLC Protocol, PCI Bus, Serial Communication, Cyclic Redundancy Check, FPGA
PDF Full Text Request
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