Rescarch And Implementation Of Pipeline Architecture For DRAM Controller In Multi-Processor SoC

At present with the network bandwidth and protocol increased quickly, thetraditional network equipment project based on GPP and ASIC cannot simultaneouslysatisfy performance and programmability requirements, therefore the networkprocessor (NP) appears and develops quickly. NP can take the advantage of both GPPand ASIC, and NP can not only meet the changing protocols and applicationrequirements, but also the flexibility to expand to provide different capabilities, so NPis the next generation of network technology. According to the characteristics ofsharing memory in NP based on MPSoC, the performance of NP will be largelydetermined on DRAM bandwidth and latency. Therefore, the design of DRAMcontroller in NP will have a profound impact.In this thesis, a pipelined DRAM controller is researched and designed accordingto the characteristics of Multi-core Multi-threaded and memory requirements of XDNP.The DRAM controller is divided into four pipelines based on function, named theinstruction fetch (IF) stage, instruction decode (ID) stage, instruction management (IM)stage and instruction release (IR) stage. IF stage is to fetch instruction from the FIFOmodule base on arbitration algorithm, and then the instruction is decoded in ID stageaccording to the type of instruction. And in IM stage, the address of adjacentinstruction is compared and control information generated based on the addressrelationship, the control information determined which DRAM command is released toDRAM by IR stage. The controller dynamic adjusts the DRAM memory strategy,either open page or close page. And it can reduce or hide memory latency and improvedata throughput.The DRAM controller is finished by hardware description language Verilog, andthe functional verification, timing verification and FPGA prototyping verification ofDRAM controller is completed to make sure the logic and timing of DRAM controlleris correct. Finally, through theoretical analysis and simulation tests, it is found thatpipelined DRAM controller had a3.6times data throughput improvement,1.2timesfrequency incensement and45%decrease in communication latency, so the pipelinedDRAM controller is suitable for network real-time processing.