Evaluation And Optimization Of Garfield On-Chip Bus Arbiter

modern realtime system is assembling more and more function modules which share identical resources on a standard backplane bus. Hence, according to real-time reqirement of system ,based on rational arbitration schedule which assign system resources in reason and control manner.,the performance of system can trend to huge improvement.Arithmetic research of arbitration is in the ascendant, at present mainstream arbitration arithmetic include Static Priority Protocol, Time-Division Multiplexed, Round-Robin Protocol, Mixed Protocol,etc.there are many arbitration circuit,include distributing arbiter and centralize arbiter.Sum up,it is to resolve priority and fairness..However selection of arbitration mechanisms in the design of SOC bus is uncertainty. By establishing Test bed based on G4 SOC and comparing simulation results ,the bus performance including bus bandwidth, worst latency,etc is evaluated.,after analyzing experiment data and confirming key performance target,a set of improving schemes are designed step by step. Evaluation result shows that mixed-priority arbitration mechanism is better than the other two arbitration mechanisms in fairness and priority and shows that lottery arbitration arithmetic guarantee assignment of bus bandwidth The result can be a good reference as far as other arbiter design is concerned. And then in allusion to the behavior character of system bus and in the interest of research impact of bus fifo limitation in different arbitration mechanism,G4 is abstracted necessarily and establish universal function model.fifo limitation of LCDC is research object and is evaluated. Finally for improving evaluation efficiency of system bus ,higher bus arbitration arithmetic model and master device model are established based matlab.evaluation result showa error is coherence between matlab and RTL simulation.So,precision of model and feasibility of evaluation method is verified.