Design And Implementation Of Heterogeneous SoC On-chip Bus For SEP8000

As the complexity of computing tasks in system-on-chip increases,especially in the intensive computing field such as artificial intelligence,heterogeneous multi-core SoCs have become an important development direction.SEP8000 is an artificial intelligence chip for ADAS(Advanced Driving Assistance System).Due to the insufficient bandwidth of the bus throughput rate and the serious memory conflicts caused by the convolutional neural network accelerator throughput requirements,the SEP8000 bus needs to be optimized for the neural network accelerator to improve its memory bandwidth utilization,to reduce memory access conflicts and to improve the overall performance of SoC.In this thesis,the bus of SEP8000 is designed,in which 64 bit bus is composed of multi-mode transmission module,multi priority polling arbitration module,bus cross switch matrix,master device bus interface,slave device bus interface and other circuit units.Through modeling and simulation of AXI Bus,analyzing its bandwidth utilization bottleneck,combined with the study of the distribution rule of CNN accelerator access memory address,it is concluded that the bandwidth utilization can be improved by transmitting smaller length data in groups Design ideas.Therefore,a skipped burst transmission mode to transmit the matrix address distribution data in the CNN accelerator memory access is proposed in this thesis,which reduces the fragmented memory access behavior of the CNN accelerator and improves the throughput and bandwidth utilization.In this thesis,through the simulation analysis and the combination of the fixed priority arbitration algorithm and the polling arbitration algorithm,the multi-priority polling arbitration algorithm is proposed,which reduces the average waiting time of the CNN accelerator memory access,and at the same time guarantees the master device Fairness.The prototype verification of the SEP80000 bus design is implemented on the KU115 FPGA verification platform provided by S2 C.In SEP8000,the BPM(BUS Performance Monitor)is designed in this thesis to compares and analyzes the bandwidth utilization and average waiting time of CNN accelerator.The test results show that the skipped transmission mode designed in this thesis can make the average increase in bandwidth utilization of SEP8000 compared with the use of AXI bus incremental burst transmission reach 27.95%;the multi-priority polling arbitration algorithm designed in this project is comparable to the polling arbitration algorithm,the average waiting time of CNN accelerator is reduced by 44.43%.The research results of this thesis have certain value in the design of heterogeneous multi-core SoC interconnection in the field of intensive computing.