Research On Router Scheduling Algorithm For Network On Chip

With the feature size of electrical devices shrinking continuously, the integrationdensity and clock frequency of the VLSI circuit increases significantly. Network onChip technology becomes the first choice of future large-scale integrated circuit, inwhich the high-performance router architecture is a good solution to improve theperformance of Network on Chip. Scheduler is the kernel component of the routerarchitecture and its performance directly affects the performance of entire network.Therefore, the main contribution of this thesis is designing an efficient schedulingalgorithm.First, recent developments of Network on Chip and basic router architecture aresurveyed with the analysis of some common scheduling algorithms in interconnectionnetwork in details. Then, the scheduling algorithms related to Network on Chip routerand the basic characteristics of several proposed scheduling algorithms are studied. Weimprove the random buffering method of input buffered Network on Chip router byusing the traditional scheduling algorithms which are used in the Internet router. Further,an Early-Packet-First combined with Round-Robin scheduling algorithm, EPF-RR, isproposed in this thesis. This algorithm takes the properties of wormhole switching andon-chip router architecture into consideration. The problem of high delay of exitingalgorithm is effectively solved. We evaluate the performance of the proposed algorithmin the OPNET simulation platform, including packet delay, throughput and energyconsumption. The simulation results demonstrate that the EPF-RR scheduling algorithmcan achieve better network performance compared with iSLIP, iSLIP-iteration, RRM,PIM in average delay and throughput under different traffic patterns. Finally, we designand verify each module of the EPF-RR algorithm in the Modelsim hardware simulationplatform to guarantee its feasibility. The verification results indicate that the proposedalgorithm works with correct functionality and meets the design requirements.