The Research Of Synchronization And Arbitration In Network On Chip

With the development of semiconductor technology, System on Chip has developed towards more processors and heterogeneity. While the shared bus architecture applied widely in the SoC presently gradually becomes the main bottleneck which restricts the system performance of CMP and can not meet the requirement of SoC. Therefore, the interconnection network is used for the SoC designs in order to resolve the communication between the on chip components, namely Network on Chip (NoC). Due to the characteristics of supporting many users to visit at the same time, high reliability and reusability, NoC is thought to be desired technology of multiprocessors.This thesis researches the technology of synchronization and arbitration.First, the reason of metastable state is introduced. To overcome the metastable state, the basic methods, two flip-flop synchronizer and asynchronous FIFO, are presented. And a asynchronous FIFO based on Grey code is developed and simulated with Modelsim 6.2. At last, two common synchronizer in GALS system are introduced—stoppable clck and locally delayed latching. Their operation modes and time sequences are also analysed.Another research focus of this thesis is arbitration in NoC. I first introduce some basic arbiters, such as mesh, tree and token ring arbiter. According to the problem of not guaranteeing the correct arbitrationorder in these arbiters, a new asynchronous ordered arbiter is proposed. In addition, it is simulated and tested with Cadence tools. Then the priority arbiter is introduced, including static priority arbiter and dynamic priority arbiter. Their principles and schematics are also presented.