Reverse Design Of EEPROM X84041 Chip

Electrically erasable programmable read-only memory (EEPROM) is mainly applied to information memory such as intelligentized IC card, single chip microcomputer, etc. It is divided into parallel and serial. Serial EEPROM has many advantages, such as little culbage, cheap cost, few connected wires. The content of my subject is the reverse design of 8K×8 serial EEPROM which is made with 1.2μm N trap CMOS technology. It is finished in Northeast Microelectronics Research Institute.The design begins at drawing logic diagram from the layout phography. According to it, I analyse the principle of the circuit and the function of logic diagram. The circuit is divided into memory matrix and periphery circuit. The memory matrix of EEPROM is 256 rows with 256 lines, which makes the detailed analysis on the core part memory cell through work principle, structure, layout and technology aspects. The periphery circuit includes protect circuit, HV circuit, high voltage producing circuit, control circuit, decoding circuit, sensitively amplificatory circuit,eight bits flip-latch and eight bits shift register. In order to ensure the correct of the circuit, the computer logic validation and simulation is made on the key function blocks. Layout design regulation means first the primary design regulation should be taken out from the primary layout photography, then the new design regulation made according to the process condition of Northeast Microelectronics Institute. The principle of placement and routing of layout should be tried hard to minish material, favor photoetching, proofread reticle conveniently and simplify technology process. The article summarizes the rule of placement and routing. Some doable methods are used to restain latch-up effect in layout. This layout adoptes double layers mental routing technology, poly-crystal silicon mostly used at stride connection, which reduces layout area, routing resistance and increases the speed of circuit.Tanner EDA and Cadence workstation are used as EDA tools in the article.