Design And Implementation Of Verification System Based On Transaction-Level Software/Hardware Co-Emulation

With the continuous development of the chip industry,the scale and complexity of the circuit are constantly increasing,and the verification of the correctness of the design often takes more time than design in the process of chip development,which makes the pure computer software simulation can not meet the needs of fast-paced chip development.At the same time,with the expansion of design scale,the difficulty and time consuming of building verification platform are increasing,which makes the research on simulation technology become one of the development focuses of IC industry.Based on the co-emulation technology,this topic designs and implements a transaction-level software/hardware co-emulation verification system with obvious simulation acceleration effect by using hardware to accelerate the simulation.Through the optimization of the transaction layer of the system,the flexibility of the system and the efficiency of the verification platform are greatly improved.This topic has mainly completed the following five aspects of work.The First,in order to realize the system design,the co-emulation technology and SCE-MI protocol are deeply studied in this thesis and the system is divided into three parts: software side,hardware side and storage space.Through the mapping of the storage space,the system can read and write the storage space in the software side to complete the software-tohardware operation without the specific circuit,which makes the actual physical channel separated from the verification system.The address of the storage space is unified for the software system and the hardware system,so that no matter how the communication channel changes in the system,there is no need to re-modify the application layer design,which makes the system have a good portability.The Second,a software/hardware co-emulation verification system is realized by using the hierarchical design method.Three kinds of interfaces in the transaction layer are designed in this thesis,and the communication between hardware and software can be completed by calling the interfaces.In order to ensure the accurate communication between the verification platform and the DUT,a clock control module is designed to freeze the DUT clock during hardware and software communication.In order to realize the real port connection,the interface channel establishment scheme is designed.PCIe is used to establish the physical layer channel and realize the communication between hardware and software.The Third,the system transaction layer is optimized.Through the design of common-proxy layer,the interface of transaction layer is simplified.Based on the thinking of object-oriented programming,this thesis designs an object-oriented method to create and use VIP.In order to solve the problems of clock jamming and data object chaos when using the interface,the design of interface coordination in transaction layer and the design of object pointer reproduction are completed.The Fourth,the VIP design method based on SCE-MI protocol is deeply studied in this thesis.Combined with the optimization scheme of transaction layer,the transaction-level VIP design paradigm based on co-emulation is designed to facilitate the design of common VIP.According to the design paradigm,the design of UART-VIP is completed,and the functions of run-time configurable,error injection,error detection,baud rate detection and frame interval practice report are realized.Finally,in order to test and analyze the performance of the system,the experiment was designed and the verification platform was built,and the conclusion was obtained that the system design was correct,the transaction layer optimization was successful and the simulation acceleration effect was obvious.Moreover,the analysis of the experimental results shows that the acceleration effect of the system can continue to improve with the increase of the DUT size and transaction information.