Research On Key Problems For Transaction Level Design Of System-on-Chip

With the development of SoC(System-on-Chip), the urgent problems to be solved in the domain of the IC(Integrated Circuit) design are the feature, the design efficiency, the design cost and the time-to-market.Under the guidance of the methodology of platform-based design, this paper analysed the advanced high-performance OCB(On-Chip-Bus) specification, investigated the most effective arbitration strategy, studied the method of modeling the transaction level model, evaluated the testing validity of a functional verification on the random testing for the transaction level, estimated the number of residual errors in the design under verification after a series of the random tests, and implemented the IP(Intellectual Property) soft core of MPMC(MultiPort Memory Controller) aim at the communication structure of the OCB. The details are as follows:For exploring the applicability of the bus protocols, the OCB of Wishbone, AMBA(Advanced Microcontroller Bus Architecture), CoreConnect, OCP(Open Core Protoco 1)were analyzed. The characteristic and the applied scope of these OCB were generalized. The AMBA which was supported by many third-parties should be adopted by the designers in many aeras.In order to solve the contradiction between the performance and the cost for the arbitration scheduling in the multi-port System-on-Chip, a new arbitration strategy that the mechanism of the earlier arbitration and the mechanism of the request waiting priority were based on the fixed priority arbitration algorithm was proposed:the mechanism of the earlier arbitration decided a new bus access request during data transfer; the mechanism of the request waiting priority set the request waiting time for the ports that the bus access requests were turn down by the arbiter. The results indicated that the bus utilization of the proposed strategy was approximately 10% higher than that of the request waiting priority strategy. This strategy can give consideration to both the priority and fairness, and gain high system performance by the low price.In order to deal with the time bottleneck of the hardware/software co-design, A method of modeling the transaction level model using SystemC was introduced. A transaction level model based on the AHB bus was developed. The experimental results revealed that the bus model was completely compliant to AHB specification. The rapidity of modeling running under transaction level was higher than that of under register transfer level.Taking the ability of the discovering mistakes, the reliability of the submission and the cost of the testing, the testing validity of the functional verification based on the random testing for the transaction level of the System-on-Chip was evaluated theoretically by the comparison approach. The evaluation result indicated that the efficiency of the partition testing was better than that of the random testing only when one or more subdomains were covered over with the area of errors, although the efficiency of the random testing was generally better than that of the partition testing.For improving reliability of the design under verification, the number of the residual errors in the design under verification after a series of the random tests was estimated. The mathematical expectation for the number of the residual errors after a series of the random tests was deduced. The testing work could be done all right.