| With the development of embedded processors,instruction-level parallel technologies such as Very Long Instruction Word and Single Instruction Multiple Data have been widely applied and developed in digital signal processors.There are many types of registers in highperformance DSP,and the number of each kind of registers is also large.Effective use of register resources is one of the core issues to exert its hardware performance.The registers in the contemporary vector DSP mainly include scalar general registers,vector general registers,and array-unit dual-usage registers,here,array-unit dual-usage register is a resource that can be read or written as a whole or individually.In addition,there are many instructions with paired registers as operands in vector DSP,so that the bit width of data processing and the bit width of memory can be effectively expanded.In order to make full use of register resources,this thesis studies the register allocation problem of high-performance vector DSP from the above two aspects.The specific research contents are as follows:(1)Research on the classification and allocation method of graph coloring registers including the code of array-unit dual-usage register names.Aiming at the vector DSP processor including the array-unit dual-usage registers and any kinds of conventional scalar registers and vector register resources,this thesis studies the register classification and allocation scheme based on the graph coloring method.By improving the construction of register allocation candidates,the construction of conflict graph and adjacency matrix,and the simplification of conflict graph in graph coloring method,an improved graph coloring register classification and allocation method is proposed.The method solves the problem of register allocation for candidates of relative register allocation by accurately analyzing the lifetimes of variables such as physical registers of the array-unit dual-usage registers,symbolic variables,and common physical registers.In this thesis,the specific aspects and algorithms of the method were described in detail,and the experimental study was conducted on a platform based on the FTM7002 DSP core.The experimental results show that the method in this thesis supports the related algorithms and obtains a large performance improvement;(2)A study of register selection methods after merging register pair requirements.In order to reduce the repeated occupancy of registers by the same type of repeated data in multiple register pairs,and to support the more flexible use of registers in input code without the hardware limitation of register pairs,This thesis studies the register assignment problem of individuals in paired register assignment candidates at a more fine-grained level.A comprehensive register selection method is proposed for both register pair allocation candidates and single register allocation candidates.The method is based on the method of position gain and preferred register,and uses three heuristics to select a suitable odd-numbered or evennumbered register for assignment of different types of candidates,which improves the success rate of register assignment to related candidates and reduces the overflow of candidates.In this thesis,the specific aspects of the method were described in detail and the experimental study was conducted on a platform based on the FT-M7002 DSP core.The experimental results show that the method in this thesis has a certain effect on improving the performance of related algorithms. |
