Design And Implementation Of Hardware Variable Length Decoder

H.264 is a new video coding standard with enhanced compression performance and is fitted for transmitting on network. Its foreground is very wide. A lot of company and research institute begin to study and make use of such new standard. Because the decoding complexity of H.264 is very high, software implementation can't decode in real time. The decoder must be implemented in hardware. In this paper, a hardware variable length decoder has been designed.NAL(Network Adaptation Layer) decoding and variable length decoding is separated into two module which are buffered by a FIFO. Four compare units are used for decoding NAL in parallel. Parallel structured variable length decoder based on barrel shifter is designed which is faster than serial structured decoder. The serial structured decoder can decode one bit per cycle. Because the structure of UVLC(Universal Veriable Length Code) is fixed,"first one detector"is designed to decode UVLC. The coefficient of CAVLC(Context Adaptive Veriable Length Code) is encoded in reverse order of zig-zag. So the coefficient of CAVLC should be stored in stack. Ping-pong structured double buffer are used for decoding CAVLC. The decoding speed can increase 22.9% in average. Pipeline and parallel structure are used in decoding intra prediction mode. Such methods can increase decoding speed.Top-down design method is used in whole design. In order to verify decoding algorithms and provide test vector, c model is designed first. Simulation is made in every design step. At last, FPGA verification and ASIC synthesis are made. The decoder can decode standard-definition video coding in real time and can decode high-definition video coding in real time if implemented in 0.18μm CMOS.