Avs And H.264 Dual Standard Variable Length Decoding Device Design,

The application of multimedia video compression technique grows very rapidly with the development of information technology and digital signal processing&transmission. Then the new video compression standard H.264 and AVS comes out. Compared with the MPEG-X and H.26X compressed video standards that were establish before, the H.264 standard can offer much better video pictures and compressing rate. So its foreground is very wide. A lot of company and research institute begin to study and make use of such new standard. Because the decoding complexity of H.264 and AVS is very high, software implementation can't decode in real time. The decoder must be implemented in hardware.This paper proposes a new architecture of Variable Length Decoder for AVS and H.264.AVS is a video coding standard, which developed by China herself, H.264/AVC is an international video coding standard, which has high performance.Research in the video decoder, which can support both AVS and H.264, has big significance.Because it can improve the function of the chip and it also has far meaning for people who will research in video decoder, which can support two or more than two video coding standards.Though AVS and H.264 have big differences in algorithms, they also have common grounds,so this design reuse some modules in VLD using the common grounds,in order to reduce the cost of hardware and enhance it's market competition.Variable length decoding is a very important technology of H.264 and AVS .This paper proposes a implementation of high speed variable length decoder for H.264 and AVS. We use a Top-Down method, firstly is system level design ,the design is separated into several parts according to the specialty of the code flow. The barrel-shifter which are based on parallel structure are used . And the C code has been used to generate the test vectors for verifying the verilog modules. The whole design has been verified by FPGA. The design consists of 14k gates when synthesized based on 0.18μm SMIC18 library. The highest frequency is 200 MHz. The design can decode the High-Definition video in real-time for H.264 and AVS .