The Design Of Variable Length Decoding In AVS And H.264 Dual Modes Video Decoder SOC

Nowadays, high definition digital TV is the active field andthe developing direction of the TV industry, in order to transportand store the digital signals efficiently, we must compress the data.AVS has been promulgated and put into effect since March 2006, itwas developed by China herself. H.264/AVC is a new video codingstandard, which has high compression ratio and peaksignal-noise-ratio, so it is very fit for transport. Both H.264 andAVS are fit for High-definition TV. We research on the video decoder,which can support both H.264 and AVS has big significance forChina's digital TV industry, because it provides and ensures thecore technology to China's video and audio industry fields, it alsosupplies the conditions for stable implement of digital TV's codingstandards and promotes the industrialization of AVS in China.In this thesis, firstly, we introduce the system of digital TV,the technology of video encoding/decoding and IC design technology,then, we provide the architecture of the whole high-definitionvideo decoder, which supports both AVS and H.264, finally, weanalysis the key design techniques and difficulties of thisarchitecture in detail, and introduce every module's function andtheir relations.As one method of entropy coding, variable length coding is veryimport in AVS and H.264, it is the main method to reduce the symbolicredundancy, and it is related to the efficiency of video compression.The main task of variable length decoder is parsing the picture'sresidual data, the speed of decoding the residual data is criticalto the speed of the whole decoder system. Variable length decoderis the first module which can read the bitstream, it can detect thevideo codes and settle the tolerance together with firmware.In this thesis, we detailed discuss removing the insert-bitsof the bit streams, variable length decoding and parsing theresidual data of the pictures.1. In order to prevent some codes confusing with the start code,we insert some extra bits into the bitstream, so in the process ofdecoding, we need to delete these extra bits before decoding theoriginal bitstream. Here we adopt five clusters of 8-bit-register,for this method, we can find both the start code and theinsert-bits ,this method is simple to construct in hardware, whichis fit for the AVS bitstream and H.264/AVC bitstream.2. The variable length decoding we discuss in this thesis's SOCis the Exp_Golomb decoding. The previous method of decoding thesigned Exp_Golomb is mapping from the unsigned Exp_Golomb.Here wedirectly mapping the signed Exp_Golomb from the bitstream, thismethod can reduce the number of cycles of decoding the signedExp_Golomb and reduce the area of this chip.3. In this thesis, we mainly introduce how to decoding thebitstream of CAVLC, we adopt the parallel method to decode a levelor run using only 3 cycles, this method enhance the speed of decodingresidual data and finally contributes to the speed of whole SOCdecoding.After design of this module, we use software as the simulatorto test the module's speed of decoding under kinds of bitstreams,compare it with the speed of playing to attain the final results,which show that the speed of decoding completely fits the real timeplaying.This design completely according to the digital IC designprocess and every step of design reserves space to the next stepin order to insure the next step can complete favorably. We use theTop-down design method and simulate every module separately thenintegrate the modules together.The whole SOC was integrated and simulated on VII6000-FPGA ofXILINX. It passed the FPGA verification. The decoder can decodestandard-definition video in FPGA. We also do ASIC synthesis forvariable length decoder module, it can decode high-definition videoin real time if use 0.18μm CMOS of SMIC.