Design Of Variable Length Decoder For AVS And H.264

Variable Length Decoder(VLD) has been widely used in kinds of video coding standards. This paper proposes a new architecture of Variable Length Decoder for AVS and H.264. AVS is a video coding standard, which developed by China herself, H.264 is an international video coding standard, which has high performance. Research in the video decoder, which can support both AVS and H.264 has big significance, because it can improve the function of the chip and it also has far meaning for people who will research in video decoder, which can support two or more than two video coding standards.Though AVS and H.264 have big differences in algorithms, they also have common grounds,so this design reuses some modules in VLD using the common grounds,in order to reduce the cost of hardware and enhance it's market competition.As this design support High-definition and Standard-definition video streams, there would be a lot of datas, if we use the structure, which can only decode one bit per cycle, it will not achive the aim to decode High-definition and Standard-definition video streams in real-time, so we adopt the Barrel-Shifter and accumulator based on parallel structure, in order to increase the decoding speed.In this paper, we use the Top-down design method in whole design. In order to verify decoding algorithms and provide test vectors for every module, we designed C model first, then do the simulation in every design step.We also analyze the circles of parsing process for AVS and CAVLC video streams.At last, we do the FPGA verification and ASIC synthesis.The decoder can decode standard-definition video in FPGA and can decode high-definition video in real time if use 0.18μm CMOS.