Degradation Research Of Metal Induced Lateral Crystallized N-Type Polysilicon Thin Film Transistors Under DC And AC Bias Stresses

This paper aims to investigate the device degradation of n-type metal induced lateral crystallized poly crystalline silicon thin film transistors under DC self-heating stress and AC stress. Considering two key aspects: different stress bias and time duration, the device degradation model are proposal to understand the observed phenomena, respectively.In self-heating stress, degradation behaviors can be divided into two stages. At the initial stage, characteristics are improved after stress. No degradation is observed. However, device performance is degraded obviously at the second stage. By the ANASY simulation, the extracted activation energy combined floating body effect interprets the change of the initial stage. However, the second stage at which threshold voltage degrades dramatically is caused by breaking or distortion of Si-Si bonds at grain boundaries due to high temperature in channel. What's more, the anomalous field mobility (μFE) is observed for the first time. The effective mobility is introduced to explain the increase of theμFE. Besides, the shift of theμFE is determined by the threshold voltage degradation.In dynamic gate pulse stress, while the pulse is applied to gate electrode. Pulse rising and falling edge, the number of pulse and base voltage are taken into account to the degradation, the results show sub-threshold region remains original states, which clearly manifest the hot carrier are generated. Finally, the mechanism under dynamic gate pulse stress is also analyzed. The hot carrier originates from two ways: one is generated by the coupled lateral electric field as pulse voltage falls into depletion region, the other comes from the depleted region of PN junction near the source/drain when a transient negative voltage is induced during the pulse falling time if all the pulse voltage immerge into strong accumulation region.