| With the development of digital signal processing technology and application, a lot of data transfers will appear frequently in modern DSP. To reduce the burthen of CPU, DMA controller must meet high-performance. Therefore, it is very important to design and realize a high-performance DMA controller.YHFT-DX is a high-performance 32-bit DSP which is independent developed by National University of Defense Technology. The frequency of DMA controller can achieve 300MHz. After studying the architecture of the DSP chip and the System-level requirements, we have thoroughly completed its logic design, functional verification, logic synthesis and code optimization by using semi-custom design method. The main topics of this thesis are as follows.1. Design and realize a DMA controller supporting a wild variety of functions. It can be configured with multi-channel based on the characteristics and requirement of function of YHFT-DX chip. It includes four common channels and a dedicated channel for the host-port interface. It supports burst-mode access, event-triggered mode access, a split-channel operation and other transport modes.It can realize various flexible operations of data transfers by combinating global registers with common registers.2. To solve the problem of long combinational logic path in the process of address calculating, we adopt finite state machine to realize the control logic of transmission. According to the idea of pipelining and the characteristic of the finite state machine, DMA controller can acquire operands ahead of time, achieve the purpose of reducing the latency overhead.3. To assure the functional correctness of DMA controller, we adopt different verification strategys, develope a relatively complete test scheme, and complete DMA controller's functional verification and timing verification.4. Completing the logic synthesis and optimization of DMA controller, finally DMA controller can meet the expected object by several iterations of optimization. |
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