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Research And FPGA Implementation Of A Reconfigurable 24 Bit Audio Oversampling DAC

Posted on:2007-06-08Degree:MasterType:Thesis
Country:ChinaCandidate:L HongFull Text:PDF
GTID:2178360185461678Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
In this paper, a high resolution DAC is designed by using ∑-△ structure. 150dB SNR is achieved with 24bits input. As a flexible audio DAC implementation method, this DAC can be applied to process audio signals in CD/DVD/HDCD/SACD mode. It can be applied to process PCM data with sampling rate of 32/44.1/48/88.2/96/192kHz and with word-length of 16/18/20/24bits which shows its good compatibility.Design and implementation of high order ∑-△ modulator is difficult because of the existence of non-linearity and instability. By learning experiences and methods from many other papers, we presented the design flow of the stable high-order high-resolution ∑-△ modulator. Based on this flow we designed a 5th-order 128-times modulator which can achieve 24bit accuracy and full input range. A high efficiency pipeline structure is imposed to implement the design. Comparing to other ordinary ∑-△ modulators our structure has advantage of simplicity and fewer computation cells. On the other hand, the clock frequency requirement is also reduced when performing under the same signal sampling rate. We cascaded 3 halfband filters and a feasible CIC filter to realize an 128x oversampling filter. Meanwhile it also has a perfect pass-band and stop-band performance. Besides, this structure is fully simplified by using CSD code in designing halfband filter.The method proposed in the paper has a reconfigurable structure. It is much easier for users to adjust its oversampling rate and order. By configuring CIC filters, we can achieve different oversampling rate at 32/64/128 in order to process different sampling rate signals ranging from 32kHz to 192kHz. By reconfiguring the modulator we can achieve a low-power consumption mode of 3th-order structure comparing to 5th-order structure under varied input word-length. Thus it will satisfy different accuracy requirement for different resolving capability.So far, this over-sampling DAC is implemented and verified by Xilinx Virtex 11 series FPGA. The result show that according to different input signals ranging from 32kHz to 192kHz, this DAC module can achieve the requirement of 24bit data transform and putout bitstream which can achieve 148dB SNR in band.
Keywords/Search Tags:DAC, reconfigurable, ∑-△modulation, pipeline, high-resolution
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