Research On Resolution Enhancement Technology Of Nanometer-scale IC

Beginning from the 0.18um technology node, the so-called Sub- Wavelength Lithography has been widely used in semiconductor processes. Because of diffraction and other physical phenomena during mask making, optical lithography and etching under Sub-Wavelength Lithography, the mask patterns are not the same as printed shapes on silicon wafer. The distortions in pattern transfer may influence the functionality and performance of IC products and lower the production yield. In order to solve the incurring manufacturability problem for higher yield, more aggressive Resolution Enhancement Technologies are developed and deployed. It becomes one of the most concerned issues for global IC industry and academia now.The theories and algorithms of Resolution Enhancement Technologies for nanometer-scale IC are the major research objects of this thesis. Basics of IC physical design and photolithography are described. A new framework of lithographic modeling and optimization along with the fast simulation algorithms are presented as well. Based on this framework and simulation algorithms, a new framework of Optical Proximity Correction approach with new scripting language is developed. An EDA tool named NanoOPC based on this framework is implemented. New methodology of phase assignment for Phase Shifting Mask and the implementation of an EDA tool named NanoPSM are thereafter introduced. Based on the improvement of algorithms for critical dimension checking, a new EDA tool named NanoSBar for Scattering Bar Insertion is implemented. The performance of these EDA tools is demonstrated by applications.