Research On Optical Proximity Correction For Deep Sub-wavelength Lithography

Being driven by Moore’s law, the transistor density of integrated circuit doubles every two years, while the performance of the circuit increases, the power consumption of the circuit decreases, and the production cost remains the same.In the past fifty years, as the key technique of IC manufacturing, the development of lithography has successfully enabled the shrinking of transistor’s size from millimeters to nanometers. The development of lithography mainly relies on new light sources with shorter wavelength. But the shrinking speed of the wavelength is much slower than that of transistor’s size.Since the250nm technology node, wavelength of light source has been greater than the feature size of the pattern to be produced, which is called as sub-wavelength lithography. Hence, resolution enhancement technologies (RETs) are developed to reduce the pattern distortion in lithography. As the most widely used and most efficient RETs, optical proximity correction (OPC) improves the fidelity of lithography by modifying the layout patterns on the lithography masks. Nowadays, the most advanced lithography technology produces IC chips with22nm/17nm feature size using193nm wavelength source. The size of produced pattern is only about tenth of the source’s wavelength, which means the lithography technology has moved into one new stage, namely the deep sub-wavelength lithography. Accordingly, deep sub-wavelength lithography has created new requirements and challenges for OPC technology. The new design style is developed; the pattern density is getting higher; and the correction is demanded to be more efficient and accurate. This dissertation proposes some new solutions for lithography simulation, dissection and hierarchy process, which are the three main steps in OPC, to fulfill the demands of deep sub-wavelength lithography. These innovations have been implemented into the proprietary ZOPC software, which has successfully processed a couple of industrial products. The main contents and innovations are summarized as follows: A fast lithography simulation method for1-D layoutIn modern IC manufacturing process, fast lithography simulation becomes one of the most significant technologies for IC layout optimization and optical system optimization. Meanwhile,1-D layout design rules are intensively studied and widely used to get better printability, as IC technology scales down to process node with "deep sub-wavelength lithography". In this dissertation, one fast lithography simulation methodology is proposed for1-D layout, taking advantage from the characteristics of partial coherent system and1-D pattern. The new methodology consists of look-up table based on1-D basis pattern, the minimum look-up table and its boundary extension, and simulation of large scale layout without division. Simulation and experiment results show that the building time of look-up table is reduced more than95%, the simulation speed for basic pattern improves about48%, and the simulation speed for large scale layout improves more than70%with highly accuracy, when the new algorithm is compared with conventional method.A novel dissection method based on circuit functionality and yieldAs the feature size of IC shrinking smaller, growing data volume of mask tremendously increases manufacture cost. The cost increase is partially due to the complicated Optical Proximity Corrections (OPC) applied on mask design. In this dissertation, a yield-aware dissection method is presented. Based on recognition of yield related mask context, the dissection result provides sufficient degrees of freedom to keep fidelity on critical sites while still retaining the frugality of modified designs.Experiments show that the final mask volume using the new method is reduced to about half of that of conventional method, and the runtime of OPC is reduced to about a quarter of the conventional method.Hybrid hierarchical processingWith the development of IC technology, the number of patterns in one set of design layout increases rapidly, which also increases the data volume of the design layout. Normally, IC design tools organize the design layout in a certain hierarchical structure, by which the access speed and process efficiency is improved, because of the data reusing. According to the different characteristics of array layout and random logic layout, this dissertation presents a hybrid hierarchy processing method to handle these two kinds of layout with different strategies.With guarantee of high correction accuracy, the new method removes the redundant correction as much as possible. As a result, the correction efficiency is improved, and the data volume of the corrected layout is reduced. The experiments show that the hybrid hierarchical processing reduces the runtime for full-chip correction by80%and the data volume of corrected layout by90%, while being compared with the conventional flatten approach. Both experiments and tape-out results verified the accuracy of this method.