System And Signal Integrity Design Of MIPS Gigabit Ethernet GAP

In order to remedy inadequate capability of current products in network security market, Suzhou-CAS IC design center (SZICC), Institute of Calculation, Chinese Academy of Sciences planed to develop MIPS gigabit Ethernet GAP hardware system. Part of the hardware design and signal integrity design for whole system is the task of paper.High-speed GAP design is an all-around project. Clock system , timing constraint, power, stack-up, bus,I/O interface, via, delay controls system test and FPGA in-system programming were lucubrated. All of them are important for hardware design. Design experience and skill for the project were used. Besides other design work, GAP bridge daughter-card and two kinds of CPU power modules (generalness and standby) were designed independently. Project schedule was speeded and readiness for unborn product upgrade was made by these work.Delay and distortion caused by signal integrity (SI) problem has become bottleneck that determines the performance of GAP system. The fact that a novel mapping from physical rule to electrical rule that is a methodology including chips package, board and architecture, and SI design based on model simulation can carry out it sufficiently was searched out. Simulation tool—SpecctraQuest (Cadence Inc.) was utilized, Flight time between chips and pre (post)-route crucial signal net were simulated, then crosstalk simulation methodology was summarized, and SI scheme for FPGA according as particularity of GAP system was introduced. Robustness of the whole system is guaranteed by all of work.Via the whole development of MIPS gigabit GAP system, not only excellent performance product for network security market is provided, but also cognition of computer architecture is strengthened, and competence of hardware design is enhanced. At the same time, SI design flow and method based on simulation analysis is acquainted, design experience is accumulated. In research interests—computer architecture and high-speed system signal integrity, some achievements have been obtained.