Analysis And Implementation Of Memory Access Scheduling

Modern processor performance increases at a rat of 60% per year, while the bandwidth of a DRAM chip increase by only 15%-20% per year, with latency improved by only 7%. Therefore Computer systems are becoming increasingly limited by memory performance. Meanwhile, as IC has marched into deep sub-micron time, power issue is considered more and more important with the prevalent development of portable electronics. Actually memories, rather than processors, consume most of the system power, and DRAM is taking up more energy than any other memories.First, We propose a dynamic SDRAM access scheduler (DSAS) according to modern SDRAM technology and kinds of memory access scheduling algorithms. Based on SDR-SDRAM technology and new version AMBA AXI bus, DSAS dynamically schedules the accesses to SDRAM and modifies Precharge Algorithm. It's applied in SDRAM Controller as a slave on AXI bus, integrating the typical AXI reordering feature, in order to improve system performance while maintaining a low level SDRAM power consumption.A modularized configurable automatic verification platform is established to verify the basic functions as above. We analyze the results and finally come to a conclusion that the memory controller using DSAS has the ability of predicting future operations and get ready for them, thus greatly hide the precharge time, which takes pretty much time in SDRAM operations;AXI bus throughput rate has improved by 19% ~ 52%, the number of active bank can be minimized at the same time, reducing the power consumption by relatively 14.3% -20.1% during frequent SDRAM accesses.We spend most of time incorporatinig a moderate memory access scheduling algorithm into powerful and complex AXI bus. In the last, we point out where there could be improved, and also the future works on these issues.